4117-8.pll analysed at 01/17/07 12:47:26
PLL Chip is ADF4117
VCO is custom
Reference is custom
Frequency Domain Analysis of PLL
Analysis at PLL output
frequency of 402.99MHz
Phase Noise Table
Freq Total VCO Ref Chip Filter
100 -79.56
-- -- -80.66
-86.03
1.00k -70.94
-- -- -78.57
-71.76
10.0k -93.41
-- -- -115.1
-93.44
100k -130.4
-- -- -171.9
-130.4
1.00M -170.4
-- -- -231.9
-170.4
Reference Spurious
Noise and Jitter
Calculations include the first 10 ref spurs
First three spurs: -300 dBc -300 dBc
-300 dBc
Phase jitter using brick wall filter
from 10.0kHz to 100kHz
Phase Jitter 0.11 degrees rms
ACP - Channel 1
Channel 1 is centred
25.0kHz from carrier with bandwidth 15.0kHz
Power in channel = -64.1dBc
---- End of
Frequency Domain Results
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Transient Analysis of PLL
Frequency change from
280MHz to 580MHz
Simulation run for 5.79ms
Frequency Locking
Did not lock to within
1.00kHz
Did not lock to within
10.0 Hz
Phase Locking (VCO Output Phase)
Did not lock to within
10.0 deg
Did not lock to within
1.00 deg
Lock Detect Threshold
Lock Detect output did not
pass 2.50 V
---- End of
Time Domain Results ----